Conventional CMOS scaling techniques have been employed to improve device and product performance in VLSI circuits for many years. However, continued aggressive device scaling is challenged by physical limitations, exponentially increasing transistor gate currents, and progressively higher power consumption induced by these changes. Moreover, transistor behavior differs across pitch and for different types of transistors such as regular Vt, zero Vt, high Vt, and low Vt.
Transistor performance may be enhanced by inducing compressive stress into the PFET channel region or tensile stress into the NFET channel region. Compressive stress causes an improvement of the hole mobility, which leads to a better performance of the PFET. To create compressive stress in the p-channel region, cavities may be etched and subsequently filled by an epitaxially grown silicon germanium (eSiGe) layer. The distance between the channel region and the eSiGe cavity, and, therefore, the degree of stress injection, can be tuned using a differential disposable spacer (DDS). The thinner the DDS, the closer the distance between the eSiGe and the channel region, and the higher the degree of stress injection. However, the thinness of the nitride layer used for the DDS is limited, as the polysilicon gate integrity also must be preserved. Currently, minimum distances between the channel region and embedded SiGe are around 50 angstroms (Å) to 80 Å of DDS spacer width inside the SRAM area.
FIGS. 1A through 1E illustrate a conventional process flow for forming an NFET 101 and a PFET 103 for 90 nanometer (nm) and 45 nm technology node devices. Adverting to FIG. 1A, gate electrodes 105 and 107 (each with a high-k dielectric, such as hafnium oxide, thereunder) and nitride caps 109 and 111, respectively, are patterned and etched on substrate 113. Gate electrodes 105 and 107 are subjected to high temperatures in an oxidizing ambient environment, forming a reoxidation (Reox) layer 115 to a thickness of 23 angstroms (Å). A nitride layer 117, such as silicon nitride, is then formed to a thickness of 60 Å to 100 Å over substrate 113, NFET 101 and PFET 103, as illustrated in FIG. 1B. In FIG. 1C, a resist 119 is formed over NFET 101 with an opening over PFET 103 (including the source and drain regions). A two-in-one anisotropic etch is performed, for example by a reactive ion etch (RIE), to form DDS 121 and cavities 123 for the PFET active areas. Adverting to FIG. 1D, resist 119 is stripped and cleaned, and eSiGe is grown in cavities 123 forming source/drain regions 125. Nitride layer 117 and DDS 121 are then removed with a sulfuric acid and hydrogen peroxide mixture (SPM)/hot ammonia and hydrogen peroxide mixture (APM) sequence, and nitride or oxide spacers 127 are formed on both NFET 101 and PFET 103, as shown in FIG. 1E. Since halo/extension region implantation is performed prior to etching cavities 123, and such areas are left unprotected when nitride layer 117 is removed, the APM destroys the implants, thereby degrading Vt behavior.
Another method for improving stress injection in the eSiGe module involves increasing the germanium (Ge) fraction within the epitaxial layer. In 45 nanometer (nm) devices, a gradation of Ge content has been employed. Ge content has been increased from 21% to 27%. However, higher Ge percentages have been found to cause stacking faults, or dislocations, and twins after epitaxy.
A need therefore exists for methodology enabling increased stress injection in the eSiGe module while decreasing Vt behavior.